Compiling xilinx simulation libraries for modelsim

Luis Ardila — Fri, 06 Sep 2013 10:30:24 GMT

We will use Simulation Library Compilation Wizard for compiling the libraries, this method is highly recommended because library compilation can be performed for more than one device family and/or language.

Open the Simulation Library Compilation Wizard. This can be accessed from Start Menu!Programs!Xilinx ISE Design Suite 13.x!ISE Design Tools!32-bit Tools. Note: If you are using 64-bit version of ModelSim use the Simulation Library Compilation Wizard from 64-bit Tools. ModelSim PE Student Version 10.x is only available in the 32-bit version.
The Select Simulator window opens up. Select the appropriate simulator (For Student Edition select ModelSim PE), enter c:nmodeltech64 10.0cnwin64 for executable location, compxlib.cfg for Compxlib Con guration File and compxlib.log for Compxlib Log File.
Next select the HDL used for simulation. If you are unsure select Both VHDL and Verilog. However, this will increase the compilation time and the disk space required.
Then select all the device families that you will be working with. Again the more number of devices, more the compilation time and the disk space required. Remember that you can always run the compilation wizard at a later time for additional devices.
The next window is for Selecting libraries for Functional and Timing Simulation. Di erent libraries are required for di erent types of simulation (behavioral, post-route, etc.). We suggest that you select All Libraries as the default option. Interested users can refer to Chapter 6 of the Xilinx Synthesis and Simulation Design Guide for additional information.
Finally the window for Output directory for compiled libraries is shown. We suggest to leave the default values that Xilinx picks. Then select Launch Compile Process.
Be patient as the compilation can take a long time depending on the options that you have chosen.
The compile process may have contain a lot of warnings but should be error-free. We have not explored the reasons behind these warnings, but they do not appear to a ect the simulation of any of our designs.
Once the process is completed, open c:nmodeltech64 10.0cnmodelsim.ini and verify if there are libraries pointing to the output directory entered in step 6. This will happen only if you have set the environment variables.

Library compilation is now complete. If you have not set the environment variables then the wizard creates a modelsim.ini in the output directory entered in step 6. By default this location is c:nXilinxn13.xnISE DSnISE. Open this le and verify that it contains the location of the libraries that were just compiled. This le should be copied into every project you create.

For more info, take a look at this pdf

put custom template format into xilinx autogenerated files

Luis Ardila — Tue, 20 Aug 2013 15:54:45 GMT

If you have your own installation of the software you could hard code your changes into the Tcl scripts that control this.

For example, the company name could be entered for VHDL modules and VHDL TBs in the following files.

– VHDL Module - line 713

C:\xilinx\13.1\ISE_DS\ISE\data\projnav\scripts\dpm_sourceTasks.Tcl

– VHDL Testbench

C:\xilinx\13.1\ISE_DS\ISE\data\testbnch2.tcl

I modified my file like this: (however I had some issues later and it wasn't doing anything, just creating blank files, If you have a solution for this please let me know, if not try this under your own risk.)

set _t [clock seconds]
set _ts [clock format $_t -format "%H:%M:%S %m/%d/%Y"]
set _date_stamp [clock -format "%m/%d/%Y"]
global xilinx::Dpm::INewSourceHdlDataID
set _iHdlData [$iNewSourceComp GetInterface $INewSourceHdlDataID]
if { $_iHdlData == 0 } {
return [dpm_Fail "interface passed to Create New Source code hook is invalid."]
}
set _entityName ""
dpm_returnOnFail { $_iHdlData GetEntityName _entityName }
set _archName ""
dpm_returnOnFail { $_iHdlData GetModuleName _archName }
dpm_Debug 11 "architecture returned is $_archName"
set _portIter 0
$_iHdlData GetPorts _portIter
puts $hFile "----------------------------------------------------------------------------------"
puts $hFile "-- Company: LBNL"
puts $hFile "-- Engineer: Luis Ardila (luis.ardila@bozica.co)"
puts $hFile "-- "
puts $hFile "-- Create Date: $_ts "
puts $hFile "-- Design Name: "
puts $hFile "-- Module Name: $_entityName - $_archName "
puts $hFile "-- Project Name: "
puts $hFile "-- Target Devices: "
puts $hFile "-- Tool versions: "
puts $hFile "-- Description: "
puts $hFile "--"
puts $hFile "-- Dependencies: "
puts $hFile "--"
puts $hFile "-- Revision: "
puts $hFile "-- Date Version Author Description"
puts $hFile "-- $_date_stamp 1.0 Luis Ardila File Created"
puts $hFile "-- Additional Comments: "
puts $hFile "--"
puts $hFile "----------------------------------------------------------------------------------"
puts $hFile "LIBRARY IEEE;"
puts $hFile "USE IEEE.STD_LOGIC_1164.ALL;"

Bozica (Posts about ISE)

Compiling xilinx simulation libraries for modelsim

put custom template format into xilinx autogenerated files