Bozica (Posts about xilinx)

Comparison between model based approach and hdl approach for a DDR3 controller

Luis Ardila — Sun, 29 May 2016 17:59:05 GMT

In an earlier post I described a simple architecture for creating a FIFO-like DDR3 controller using Vivado's block design integrator tool. This tool is of great use when interconnecting various IP Cores with standard interfaces as it was the case. This however is usually not the most optimal implementation for a given design.

The usage of the DataMover in the architecture mentioned previously still required a FSM written in HDL language to control the different commands and achive the desired behavior. That FSM dealed with data sizes, addresses and status reports to move data from the AXI-S to the AXI-MM domain and viceversa.

After a more detailed review of the AXI-MM protocol the FSM used to issue commands to the DataMover could be easily modified to instead handle the AXI-MM interface of the Xilinx's DDR IP Core and therefore eliminating the need of the DataMover, the AXI-Interconnect and the Block Design tool.

The following image represents the resource utilization for both approaches.

Comparizon of resources utilization between both approaches

The case a) represents the utilization of the different blocks in the model based approach

Yellow: HDL Block to control the DataMover
Purple: DDR Controller Block with AXI-MM Interface
Red: DataMover Block
Green: AXI-Interconnect Block
Blue: Input and Output FIFOs for DDR Controller and extra logic for PCIe communication

The case b) represents the utilization of the different blocks in the HDL approach

Yellow: HDL Block to control the DataMover
Purple: DDR Controller Block with AXI-MM Interface
Blue: Input and Output FIFOs for DDR Controller and extra logic for PCIe communication

Resource
Slice LUTs	19181	12557
Slice Registers	19262	10262
Muxes	421	4134
Slices	8542	5017
LUT FF Pairs	25096	15534
Block RAM tiles	31.5	15.5
% of Design	80 %	70 %

HDL approach (b) uses in average only 70 % of the resources of the model based approach (a)

FIFO-like Controller for DDR3 Memory

Luis Ardila — Sun, 29 May 2016 15:59:02 GMT

In an earlier post Correctly Matching Xilinx Native FIFOs to Streaming AXI FIFOs, I mentioned the advantages of interconnecting Xilinx's Native FIFOs to AXI-Streaming FIFOs and some special considerations on how to do it. Now, I would like to show a simple architecture to use the DDR3 memory as a Native FIFO.

The intention of this post is to show a possible implementation for creating a DDR3 Memory Controller which effectively remove from the end user the address handling for read and write operations and simply delivers a FIFO behaviour to the end user. There are many advantages on using a large DDR3 Memory (in the range of 1 to 4 GB) as regular FIFO. RAM Memory blocks on FPGA devices are very limited, therefore it is often required to use external devices for such purpose.

FIFOs are tipically used in FPGA designs as temporal buffers to accomodate temporal waiting states from the different logic blocks. It provides a great oportunity to cross clock domains as well. But in general they are very useful when we would like to buffer detector data which later will be used as part of an algorithm calculation when all calculations have concluded and then it is required to substract the original value from the calculated data several clock cycles after the original value arrived.

In this scenario, the limiting factor comes from the size of the FIFO that could be implemented entirely inside an FPGA. Internal storage is very small (~tens of MB) and therefore the need of designing a simple comtroller for encapsulating DDR3 transactions into input and output FIFO ports.

General architecture of the design

Using the Xilinx IP integrator tool, the previours design was implemented along with a custom FSM (represented by the DataMover Controller Block in the image) to control the data flow written in Verilog and integrated with the rest of the block design. The Verilog file contains two simple state machines for writing and reading operations of the DDR considering the current status of the input and output FIFOs.

Finite state machine from streamming domain to DDR3 memory mapped domain.

The transfer of data from the input FIFO to the S2MM AXI-S port of the DataMover is managed by the state machine mentioned above. When the input FIFO is empty the FSM remains in the IDLE state. Once some data has arrived it moves to the FILLING FIFO state where it waits until one of two conditions are met. First the data size contained in the input FIFO has to be greater or equal to 4 kB or second the Timer signal has reached its maximum value. If one of those two conditions are met, then the FSM proceeds to the SEND CMD and SEND DATA states. The timer signal allows the system to not remain locked in case that less than 4 kB of data have arrived. The filling level of the FIFO is measured using the "More Accurate Data Counts" feature available in the "First Word Fall Through" FIFO. In this way there is an accurate representation of the data contained inside and therefore the size of the data to transfer can be calculated appropriately.

In the SEND DATA state the FSM issues read requests to the input FIFO and sends the data to the AXI-S interface of the DataMover following the special considerations mentioned in Correctly Matching Xilinx Native FIFOs to Streaming AXI FIFOs. The FSM takes care that the exact size of data declared in the SEND CMD state is read from the FIFO and transfered to the DataMover. Once the data has been transfered in its totality the state machine goes back to the initial IDLE state. It is also worth mentioning that the FIFO can receive more data at the same time it is reading and transferring to the DataMover. The state machine allows an accurate data size management so that no data is repeated or lost during the transmission, accurate data counters also provide a higher level of reliability to the overall transfer.

Finite state machine from DDR3 memory mapped domain to streamming domain.

The state machine will remain in the IDLE state until the writing address pointer is different from the reading address pointer. When the FSM is in the SEND CMD state it sends a read request with the appropriate size, but if the data to be read is larger than 8 MB, it is necessary to issue multiple commands with maximum "bytes to transfer" (bbt) being 8 MB. This limitation comes from the DataMover itself, the command have only 23 bits for the bbt parameter.

Configuring Xilinx FPGAs with impact in batch mode

Luis Ardila — Sat, 05 Mar 2016 23:12:22 GMT

There are times during the development phase of a project that it is necesary to configure the FPGA with several different versions of the Firmware as new features are added and tests with the hardware are required.

To some designers the impact software have too many pop-out windows asking for unrelevant information when all we want is to configure the device. By using the batch mode all gets reduce to a single terminal instruction.

impact -batch script.cmd

I created a simple bash script which takes the .bit filename and replace it in a general script template to allow configuration of the device with different filenames without having to modify the script by hand every time.

./fpga_config.sh -f FILENAME.bit

You can find the code and a sample batch script in github

git clone https://github.com/leardilap/FPGA_Conf.git

Installing Digilent USB-JTAG Programming Cable Drivers

Luis Ardila — Sat, 05 Mar 2016 22:33:47 GMT

Installing impact and the Digilent configuration cable drivers are not always a smooth task. The USB-JTAG cable is not supported directly with the driver provided by Xilinx in the Lab Tools, therefore it is necesarry to install external drivers.

In the Xilinx forums it is possible to find a great number of questions regarding the installation of the cable drivers but most of those solutions do not really work. The following is a proven simple set of instructions that will install correctly the drivers.

First you need to download the Lab Tools from the Xilinx website, then:

Install libraries

zypper in fxload
cnf fxload
zypper in libusb-0_1-4 libusb-1_0-0 libusbmuxd-devel libusbmuxd2

Install impact

tar -xvf Xilinx_LabTools_14.7_1015_1.tar
cd Xilinx_LabTools_14.7_1015_1
sudo ./xsetup

Install official cable drivers

cd /opt/Xilinx/14.7/LabTools/common/bin/lin64/digilent
sudo ./install_digilent.sh

Install .hex and rules in correct locations

cd /opt/Xilinx/14.7/LabTools/common/bin/lin64

sed xusbdfwu.rules -e 's:TEMPNODE:tempnode:g
s:SYSFS:ATTR:g
s:BUS:SUBSYSTEM:g
' > /etc/udev/rules.d/xusbdfwu.rules

cp xusb*.hex /usr/share

udevadm control --reload-rules

Run impact

source /opt/Xilinx/14.7/LabTools/settings64.sh
impact &

Correctly Matching Xilinx Native FIFOs to Streaming AXI FIFOs

Luis Ardila — Thu, 28 Jan 2016 21:35:44 GMT

It could be unusual to connect a Xilinx's Native FIFO interface to a streaming AXI FIFO, but sometimes this small trick might be necessary. For instance, the Native FIFOs can be configured with non-symmetric aspect ratios if the Independent Clocks Block RAM configuration is selected. This feature is very useful to appropriately cross different clock domains. For instance the input port of the FIFO could be at 100 MHz with a data width of 256 bits and the output at 50 MHz with a data with of 512 bits.

The AXI-Streaming FIFOs don't have the ability to configure different aspect ratios between the input and output ports, but they are compatible with different AXI standard IP blocks provided by Xilinx. The IP integrator tool of Vivado allows the easy interconnection between IP Cores using a graphical interface.

To demonstrate a case where this might be useful, a DDR3 controller is to be design using the IP Cores provided by Xilinx. The idea is to achieve a behavior so that a simple very large FIFO is instantiated instead of having to deal with addresses in the DDR3 Memory. For this the DataMover IP Block is selected, effectively translating the Address mapped domain (AXI-MM) into a streaming domain (AXI-S). This post will go only in the detail of interconnecting two Native FIFOs with different aspect ratios between input and output to the AXI-S interfaces of the DataMover which is the same interface as if it was a AXI-Streaming FIFO.

The Block Design tool of Vivado is not enough to implement some simple connections containing some logic gates, therefore it is necessary to create a small Verilog or VHDL file which do the connections for us. Also, in the case of using the Datamover as in the image, it also issues the commands and checks for the statuses.

Block Design

For a simple Native FIFO to AXI FIFO these are the only connections we would need to implement.

assign s_axis_s2mm_tkeep = 64'hFFFF_FFFF_FFFF_FFFF;

assign s2mm_fifo_rd_en = s_axis_s2mm_tready & ~s2mm_fifo_empty;
assign s_axis_s2mm_tvalid = s_axis_s2mm_tready & s2mm_fifo_valid & ~s2mm_fifo_empty;

assign m_axis_mm2s_tready = ~mm2s_fifo_prog_full;
assign mm2s_fifo_wr_en = m_axis_mm2s_tready & m_axis_mm2s_tvalid;

Waveform of the involved signals created with Wavedrom

One final remark is that the input FIFO, to convert from Native to Streaming FIFO it is necessary to be First Word Fall Through, this will correctly align the s_axis_s2mm_tready signal to the s_axis_s2mm_tvalid. For the output FIFO from Streaming to Native it is not required to have this feature, and probably we do not even want it, just by having the Valid signal when data is available is sufficient for the subsequent stages.

Compiling xilinx simulation libraries for modelsim

Luis Ardila — Fri, 06 Sep 2013 10:30:24 GMT

We will use Simulation Library Compilation Wizard for compiling the libraries, this method is highly recommended because library compilation can be performed for more than one device family and/or language.

Open the Simulation Library Compilation Wizard. This can be accessed from Start Menu!Programs!Xilinx ISE Design Suite 13.x!ISE Design Tools!32-bit Tools. Note: If you are using 64-bit version of ModelSim use the Simulation Library Compilation Wizard from 64-bit Tools. ModelSim PE Student Version 10.x is only available in the 32-bit version.
The Select Simulator window opens up. Select the appropriate simulator (For Student Edition select ModelSim PE), enter c:nmodeltech64 10.0cnwin64 for executable location, compxlib.cfg for Compxlib Con guration File and compxlib.log for Compxlib Log File.
Next select the HDL used for simulation. If you are unsure select Both VHDL and Verilog. However, this will increase the compilation time and the disk space required.
Then select all the device families that you will be working with. Again the more number of devices, more the compilation time and the disk space required. Remember that you can always run the compilation wizard at a later time for additional devices.
The next window is for Selecting libraries for Functional and Timing Simulation. Di erent libraries are required for di erent types of simulation (behavioral, post-route, etc.). We suggest that you select All Libraries as the default option. Interested users can refer to Chapter 6 of the Xilinx Synthesis and Simulation Design Guide for additional information.
Finally the window for Output directory for compiled libraries is shown. We suggest to leave the default values that Xilinx picks. Then select Launch Compile Process.
Be patient as the compilation can take a long time depending on the options that you have chosen.
The compile process may have contain a lot of warnings but should be error-free. We have not explored the reasons behind these warnings, but they do not appear to a ect the simulation of any of our designs.
Once the process is completed, open c:nmodeltech64 10.0cnmodelsim.ini and verify if there are libraries pointing to the output directory entered in step 6. This will happen only if you have set the environment variables.

Library compilation is now complete. If you have not set the environment variables then the wizard creates a modelsim.ini in the output directory entered in step 6. By default this location is c:nXilinxn13.xnISE DSnISE. Open this le and verify that it contains the location of the libraries that were just compiled. This le should be copied into every project you create.

For more info, take a look at this pdf

put custom template format into xilinx autogenerated files

Luis Ardila — Tue, 20 Aug 2013 15:54:45 GMT

If you have your own installation of the software you could hard code your changes into the Tcl scripts that control this.

For example, the company name could be entered for VHDL modules and VHDL TBs in the following files.

– VHDL Module - line 713

C:\xilinx\13.1\ISE_DS\ISE\data\projnav\scripts\dpm_sourceTasks.Tcl

– VHDL Testbench

C:\xilinx\13.1\ISE_DS\ISE\data\testbnch2.tcl

I modified my file like this: (however I had some issues later and it wasn't doing anything, just creating blank files, If you have a solution for this please let me know, if not try this under your own risk.)

set _t [clock seconds]
set _ts [clock format $_t -format "%H:%M:%S %m/%d/%Y"]
set _date_stamp [clock -format "%m/%d/%Y"]
global xilinx::Dpm::INewSourceHdlDataID
set _iHdlData [$iNewSourceComp GetInterface $INewSourceHdlDataID]
if { $_iHdlData == 0 } {
return [dpm_Fail "interface passed to Create New Source code hook is invalid."]
}
set _entityName ""
dpm_returnOnFail { $_iHdlData GetEntityName _entityName }
set _archName ""
dpm_returnOnFail { $_iHdlData GetModuleName _archName }
dpm_Debug 11 "architecture returned is $_archName"
set _portIter 0
$_iHdlData GetPorts _portIter
puts $hFile "----------------------------------------------------------------------------------"
puts $hFile "-- Company: LBNL"
puts $hFile "-- Engineer: Luis Ardila (luis.ardila@bozica.co)"
puts $hFile "-- "
puts $hFile "-- Create Date: $_ts "
puts $hFile "-- Design Name: "
puts $hFile "-- Module Name: $_entityName - $_archName "
puts $hFile "-- Project Name: "
puts $hFile "-- Target Devices: "
puts $hFile "-- Tool versions: "
puts $hFile "-- Description: "
puts $hFile "--"
puts $hFile "-- Dependencies: "
puts $hFile "--"
puts $hFile "-- Revision: "
puts $hFile "-- Date Version Author Description"
puts $hFile "-- $_date_stamp 1.0 Luis Ardila File Created"
puts $hFile "-- Additional Comments: "
puts $hFile "--"
puts $hFile "----------------------------------------------------------------------------------"
puts $hFile "LIBRARY IEEE;"
puts $hFile "USE IEEE.STD_LOGIC_1164.ALL;"