Linking libraries to simulate verilog altera megacores

In Modelsim right click on the source file that contains the declaration of the Megacore. Then, select the Properties option.

There select the Verilog & SystemVerilog tab, click on the Library File button in the lower part, and select the file where the component is declared.

Here be careful to select the .v file as it needs to compile it and add it to the work directory.

adding library to compiler options